Some embodiments of the present disclosure relate generally to frequency acquisition and bang-bang phase detectors used in clock and data recovery (CDR).
Serial links include a transmitter connected to a receiver via a channel. The receiver generally includes a circuit configured to generate a clock that aligns with the phase of the incoming data.
FIG. 1 depicts a related art CDR circuit configured to align a locally generated clock with an incoming data signal.
Referring to FIG. 1, a related art CDR system 100 includes data and crossing slicers 110 that sample the incoming data and provide the data to the bang-bang phase detector 120. The bang-bang phase detector 120 determines if the phase of the clock generated by a voltage controlled oscillator (VCO) 130 is in alignment (e.g., in-phase) with the incoming data. A bang-bang phase detector has 3 states that include the phase being early, late, or that there is no useful information (e.g., there is no data transition required to determine phase alignment). Based on the current state, the bang-bang phase detector 120 outputs an up value or a down value. The up and down signals are provided to a charge pump 140 which activates a switch to increase or decrease the control voltage of the VCO 130. For example, when an up signal is received at the charge pump 140, the charge pump increases the control voltage of the VCO 130 and the frequency of the clock generated is increased. Similarly, when a down signal is received at the charge pump 140, the charge pump 140 decreases the control voltage of the VCO 130 and the frequency of the clock generated is decreased.
In order to properly lock the phase, the VCO 130 needs to generate a clock with a frequency close to the data rate. Thus, frequency acquisition 150 is used to set the initial clock. The frequency acquisition circuit 150 receives a clock output from the VCO 130 and provides a voltage output to increase or decrease the clock frequency generated by the VCO 130.
In the past, a number of methodologies have been employed for frequency acquisition. For example, frequency acquisition has been performed using a frequency acquisition circuit that may employ a phase-frequency detector (PFD), a rotational frequency detector, or a counter-based frequency detector. These prior systems, however, have suffered from numerous disadvantages. For example, a PFD is not suitable for digital CDR. Both PFDs and rotational frequency detectors do not work well with low-swing signals transmitted from the transmitter. Counter-based frequency detectors need multi-bit counters and various arithmetic operations to function requiring too much space and complexity and furthermore may produce a multi-bit frequency error and are therefore difficult to implement.
Thus, a method of providing accurate frequency acquisition that operates on input data after translation to CMOS (e.g., after the slicers) and without the use of multi-bit arithmetic operations is needed.
The above information is only for enhancement of understanding of the background of embodiments of the present disclosure, and therefore may contain information that does not form the prior art.